1. Field of the Invention
The present invention relates generally to the field of semiconductor devices, and more particularly to a patterned structure of a semiconductor device and a method of making the same.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET is able to increase the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be controlled more effectively. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
However, the design of the current fin-shaped structures may cause some drawbacks even though the fin-shaped structures are widely adopted in the semiconductor device beyond 20 nm node. For instance, an electrical isolation structure is often disposed between two of the adjacent FinFET devices to electrically isolate these FinFET devices. However, due to the existence of the electrical isolation structure, additional space must be provided between two of the adjacent FinFET devices, which inevitably causes the reduction in the integration of the whole semiconductor device.
Accordingly, there is still a need to provide an improved semiconductor device and a method of making the same.